Presentation at SYNCHRON'12
Modeling of time in discrete-event simulations of systems on a chip
Matthieu Moy, VERIMAG
The SystemC/TLM technologies are widely accepted in the industry for fast system-level simulation. An important limitation of SystemC regarding performance is that the reference implementation is sequential, and the official semantics makes parallel executions difficult. As the number of cores in computers increase quickly, the ability to take advantage of the host parallelism during a simulation is becoming a major concern. Most existing work on parallelization of SystemC targets cycle-accurate simulation, and would be inefficient on loosely timed systems since they cannot run in parallel processes that do not execute simultaneously. We propose an approach that explicitly targets loosely timed systems, and offers the user a set of primitives to express tasks with duration, as opposed to the notion of time in SystemC which allows only instantaneous computations and time elapses without computation. The approach was first implemented in an experimentation platform called jTLM, and then as a library that runs on top of any (unmodified) SystemC implementation, which lets legacy SystemC code continue running as-it-is. It exploits this notion of duration to run the simulation in parallel. This allows the user to focus on the performance-critical parts of the program that need to be parallelized.