Presentation at SYNCHRON'12
Guided tour of the P2012 TLM model: simulation speed and timing accuracy
Claude Helmstetter, CEA LETI
As all complex SoCs, the P2012 chip has its SystemC/TLM model. Focusing on the heterogeneous variant of P2012, which merges ideas from the classic homogeneous P2012 chip and CEA NoC-based heterogeneous chips, we show how this TLM model deals with the simulation speed vs timing accuracy tradeoff. A key idea is to provide one model with many options allowing to tailor the speed and accuracy according to the use case. For this end, some modules and communication protocols are available at many levels of abstraction, such as the TLM ANoC protocol. Moreover, the TLM model uses temporal decoupling to reduce the number of context switches, and thus avoid simulation slowdowns. While memory-mapped transactions use existing techniques, a new FIFO implementation had to be developed to apply temporal decoupling efficiently to stream-based communications. Finally, we illustrate the work above by showing how this model has been used to evaluate new stream-based communication protocols and their control software.